In recent years, active-matrix display devices with increasingly high resolutions have been developed. In such devices, a plurality of image signal line driver circuits are sometimes provided to distribute the driving load. In this case, image signals from another device are input to a display control circuit that includes a timing controller and then transmitted to each of the image signal line driver circuits. There are various well-known technologies for transmitting these image signals.
In one example of such a technology, a common bus line is provided for the plurality of image signal line driver circuits, and the image data for each image signal line driver circuit is sent via this bus line. This scheme is known as a “multidrop” scheme. In another example of such a technology, signal lines are formed connecting between the display control circuit and the image signal line driver circuits in a one-to-one relationship, and the image data for each image signal line driver circuit is sent directly from the display control circuit via these signal lines. This scheme is known as a “P to P” scheme.
However, the multidrop scheme described above typically requires use of relatively large transmission cables, connectors, substrates, and the like because the bus line includes a large number of signal lines, which tends to result in high costs. Moreover, while the P to P scheme described above does not require the bus line used in the multidrop scheme, the number of signal lines for transmitting image data must correspond to the number of image signal line driver circuits, and this number is ultimately limited.
Japanese Patent Application Laid-Open Publication No. 2006-30949, for example, discloses a configuration for solving these problems in which n driver chips (which are equivalent to the image signal line driver circuits) that can respectively output pixel signals (the image signals) to the next stage are cascade-connected together. Moreover, Japanese Patent Application Laid-Open Publication No. 2006-330029, for example, discloses a configuration in which a plurality of display driver devices (which are equivalent to the image signal line driver circuits) that can respectively output a plurality of signals to the next stage via a plurality of transmission paths are cascade-connected together. In these conventional configurations, cascade-connecting a plurality of image signal line driver circuits together makes it possible to form a large number of image signal line driver circuits while only using a small number of signal lines.